In general, nonvolatile semiconductor memory devices can be classified into two groups: electrically programmable read-only memories (EPROMs) and electrically erasable and programmable read-only memories (EEPROMs). Each of these devices, EPROM and EEPROM, usually includes a floating gate element which is electrically isolated from other conductors in the device and which is used to store electrons in varying amounts. The storage of electrons on the floating gate in varying amounts provides a means for storing binary digital information. For example, a charge level above a predetermined level may be used to represent a first binary state whereas a charge level below the predetermined level may be used to represent a second binary state.
The EPROM and EEPROM devices differ in one respect by the way each device introduces electrons onto the floating gate and by the way each device removes electrons from the floating gate. For introducing electrons onto the floating gate, the EPROM device generally uses channel hot electron injection whereas the EEPROM device generally uses electron tunneling from an auxiliary conductor by use of the Fowler-Nordheim electron-tunneling mechanism. For removing electrons from the floating gate, the EPROM device generally uses ultraviolet-light exposure whereas the EEPROM device generally uses electron tunneling from the floating gate to an auxiliary conductor, which may be the same auxiliary conductor used in the programming operation or a different auxiliary conductor.
Presently in the non-volatile memory art, EPROM devices have a smaller cell size and a more simple cell design than EEPROM devices. EPROM devices can, therefore, be manufactured with higher densities and lower costs than EEPROM devices. In contrast, EEPROM devices provide the capabilities of erasing single bytes or pages of the memory array instead of having to erase the entire array and of performing this erasure electrically in the system environment rather than having to expose the memory device to ultra-violet (UV) light outside the system environment. A non-volatile memory device which possess these capabilities, along with a capability to electrically program a byte or page selectively, is often referred to as a `full-featured` non-volatile memory device. To provide all of these capabilities, EEPROM devices have one or more control electrodes for capacitively `steering` the potential on the floating gate. Such control electrodes increase the cell size of the EEPROM cell. Separate select gates and lithographically-defined tunnel oxide areas also increase the size of the typical EEPROM cell relative to the EPROM cell. As such, there is currently a trade-off in the non-volatile memory art between the compact size of an EPROM non-volatile memory cell and the `full-featured` capabilities of an EEPROM non-volatile memory cell.
There is, therefore, a great need to provide full-featured capabilities in a non-volatile memory device while achieving a more compact memory cell size. The present invention is directed toward filling this need.
One prior art solution to this problem is shown in the reference Guterman, et al., "An Electrically Alterable Nonvolatile Memory Cell Using a Floating-Gate Structure," IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 2, April 1978. This reference teaches a nonvolatile electrically alterable memory cell (called an "EAROM") having a floating gate spaced from the substrate to form an n-channel floating-gate transistor between a source region and a drain region. The reference further teaches a control gate having a first portion disposed above the substrate and a second portion disposed above the floating gate to provide a large capacitive coupling between the control gate and the floating gate. The first portion of the control gate is further disposed adjacent to the floating gate, the floating gate and control gate thereby forming a channel between source and drain. This channel is divided into two serial sections, one under the control of the floating-gate and the other under the direct influence of the control gate. Programming of the floating gate takes place through a direct hot-electron emission mechanism from channel to floating gate. Erasure occurs through high-field emission from floating gate to control gate. This reference teaches a high capacitive coupling between control gate and floating gate so that a substantial amount of voltage is coupled to the floating gate from the control gate during programming. This coupling of high voltage is used to increase the number of electrons tunneled from the channel to the floating gate during programming, i.e., it is used to increase tunneling efficiency. However, a consequence of using high voltage on the control gate to raise the floating gate voltage during programming is the occurrence of an undesirable erasure process during programming. This effect competes with programming of the floating gate. In this competing erasure process, electrons are also caused to tunnel from the floating gate to the control gate during programming due to the high voltage existing on the control gate during programming, thereby countering the increased tunneling from the substrate to the floating gate. In contrast, the present invention eliminates this competing erasure process.